ARM Ltd. CMSDK_CM7 2025.07.11 ARM 32-bit Cortex-M7 based device CM7 r0p0 little 3 false 8 32 DUALTIMER Dual Timer DUALTIMER 0x40002000 0x0 0x3C registers n DUALTIMER Dual Timer interrupt 10 TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF FPGAIO FPGA System Control I/O FPGAIO 0x40028000 0x0 0x100 registers n BUTTON Button Connections 0x8 32 read-write n 0x0 0xFFFFFFFF BUTTON0 0 1 Off BUTTON is off 0 On BUTTON is on 1 BUTTON1 1 2 Off BUTTON is off 0 On BUTTON is on 1 CLK100HZ 100Hz Up Counter 0x14 32 read-only n 0x0 0xFFFFFFFF CLK1HZ 1Hz Up Counter 0x10 32 read-only n 0x0 0xFFFFFFFF COUNTER Cycle up counter 0x18 32 read-write n 0x0 0xFFFFFFFF LED LED Connections 0x0 32 read-write n 0x0 0xFFFFFFFF LED0 0 1 Off LED is off 0 On LED is on 1 LED1 1 2 Off LED is off 0 On LED is on 1 MISC Misc. Control 0x4C 32 read-write n 0x0 0xFFFFFFFF ADC_SPI_nCS 7 8 CLCD_BL_CTRL 6 7 CLCD_CS 0 1 CLCD_RD 5 6 CLCD_RESET 3 4 CLCD_RS 4 5 SHIELD0_SPI_nCS 8 9 SHIELD1_SPI_nCS 9 10 SPI_nSS 1 2 PRESCALER Reload value for prescaler counter 0x1C 32 read-write n 0x0 0xFFFFFFFF PSCNTR Prescale Counter 0x20 32 read-write n 0x0 0xFFFFFFFF GPIO0 general-purpose I/O GPIO 0x40010000 0x0 0x3C registers n GPIO0 GPIO 0 combined interrupt 6 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO1 general-purpose I/O GPIO 0x40011000 0x0 0x3C registers n GPIO1 GPIO 1 combined interrupt 7 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF SCC Serial Communication Controller SCC 0x4002F000 0x0 0x1000 registers n AID 0xFF8 32 read-only n 0x0 0xFFFFFFFF FPGA_BUILD FPGA Build Number 24 32 MPS2_REV V2M-MPS2 target Board Revision (A=0,B=1,C=2) 20 24 NUM_CFG_REG Number of SCC configuration register 0 8 CFG_REG0 0x0 32 read-write n 0x0 0xFFFFFFFF REMAP 1 = REMAP Block RAM to ZBT 0 1 CFG_REG1 0x4 32 read-write n 0x0 0xFFFFFFFF MCC_LED0 MCC LEDs: 0 = OFF 1 = ON 0 1 Off LED is off 0 On LED is on 1 MCC_LED1 MCC LEDs: 0 = OFF 1 = ON 1 2 Off LED is off 0 On LED is on 1 MCC_LED2 MCC LEDs: 0 = OFF 1 = ON 2 3 Off LED is off 0 On LED is on 1 MCC_LED3 MCC LEDs: 0 = OFF 1 = ON 3 4 Off LED is off 0 On LED is on 1 MCC_LED4 MCC LEDs: 0 = OFF 1 = ON 4 5 Off LED is off 0 On LED is on 1 MCC_LED5 MCC LEDs: 0 = OFF 1 = ON 5 6 Off LED is off 0 On LED is on 1 MCC_LED6 MCC LEDs: 0 = OFF 1 = ON 6 7 Off LED is off 0 On LED is on 1 MCC_LED7 MCC LEDs: 0 = OFF 1 = ON 7 8 Off LED is off 0 On LED is on 1 CFG_REG2 0x8 32 read-only n 0x0 0xFFFFFFFF CFG_REG3 0xC 32 read-only n 0x0 0xFFFFFFFF MCC_SWITCHE0 MCC SWITCHES: 0 = OFF 1 = ON 0 1 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE1 MCC SWITCHES: 0 = OFF 1 = ON 1 2 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE2 MCC SWITCHES: 0 = OFF 1 = ON 2 3 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE3 MCC SWITCHES: 0 = OFF 1 = ON 3 4 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE4 MCC SWITCHES: 0 = OFF 1 = ON 4 5 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE5 MCC SWITCHES: 0 = OFF 1 = ON 5 6 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE6 MCC SWITCHES: 0 = OFF 1 = ON 6 7 Off Switch is off 0 On Switch is on 1 MCC_SWITCHE7 MCC SWITCHES: 0 = OFF 1 = ON 7 8 Off Switch is off 0 On Switch is on 1 CFG_REG4 0x10 32 read-only n 0x0 0xFFFFFFFF BRDREV Board Revision 0 4 CFG_REG5 0x14 32 read-write n 0x0 0xFFFFFFFF DEBUG Debug: 0 = Serial Wire Debug 1 = JTAG 5 6 CFG_REG6 0x18 32 read-only n 0x0 0xFFFFFFFF CFG_REG7 0x1C 32 read-only n 0x0 0xFFFFFFFF DLL DLL Lock Register 0x100 32 read-write n 0x0 0xFFFFFFFF LOCKED Complete Flag 0 1 LOCKED_MASKED Error Flag 24 32 LOCK_UNLOCK Complete Flag 16 24 ID 0xFFC 32 read-only n 0x0 0xFFFFFFFF APP_NOTE_VAR Application note IP variant number 20 24 APP_REV Application note IP revision number 0 4 IMPLEMENTER_ID Implementer ID: 0x41 = ARM 24 32 IP_ARCH IP Architecture: 0x4 = AHB 16 20 PRI_NUM Primary Part Number: 383 = AN383 4 12 SYS_CFGCTRL 0xA8 32 read-write n 0x0 0xFFFFFFFF DEVICE Device (value of 0/1/2 for supported clocks 0 12 RFUNCVAL Function Value 20 26 RW_ACCESS Read/Write Access 30 31 START Start: generates interrupt on write to this bit 31 32 SYS_CFGDATA_OUT 0xA4 32 read-write n 0x0 0xFFFFFFFF SYS_CFGDATA_RTN 0xA0 32 read-write n 0x0 0xFFFFFFFF SYS_CFGSTAT 0xAC 32 read-write n 0x0 0xFFFFFFFF COMPLETE Complete Flag 0 1 ERROR Error Flag 1 2 SPI SPI SPI 0x40027000 0x0 0x40 registers n SPI Combined SPI 0, SPI 1 Interrupt 11 SPCLK SPI Clock Configuration 0x4 read-write n 0x0 0xFFFFFFFF SPCON SPI Configuration 0x6 read-write n 0x0 0xFFFFFFFF CPHA 4 5 CPOL 3 4 MSTRS 2 3 SPEN 0 1 SPR0 6 7 SPR1 5 6 SSDIS 1 2 SPDAT SPI Data 0x2 read-write n 0x0 0xFFFFFFFF SPSTAT SPI Status 0x0 read-write n 0x0 0xFFFFFFFF TIMER0 Timer 0 TIMER 0x40000000 0x0 0x10 registers n TIMER0 Timer 0 interrupt 8 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock s disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1 Timer 0 TIMER 0x40001000 0x0 0x10 registers n TIMER1 Timer 1 interrupt 9 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock s disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF UART0 UART 0 UART 0x40004000 0x0 0x14 registers n UART0_TX UART 0 Transmit Interrupt 1 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART1 UART 0 UART 0x40005000 0x0 0x14 registers n UART1_TX UART 1 Transmit Interrupt 3 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART2 UART 0 UART 0x40006000 0x0 0x14 registers n UART2_TX UART 2 Transmit Interrupt 5 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART3 UART 0 UART 0x40007000 0x0 0x14 registers n UART3_TX UART 3 Transmit Interrupt 19 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART4 UART 0 UART 0x40009000 0x0 0x14 registers n UART4_TX UART 4 Transmit Interrupt 21 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear WDT Watchdog Timer WDT 0x40008000 0x0 0xC04 registers n WDT Watchdog Interrupt 0 WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x20 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable ENable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable ENable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF